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RT8234A 1 ds8234a-01 june 2011 www.richtek.com applications z notebook computers z cpu core supply z chipset/ram supply as low as 0.75v single synchronous buck pwm controller with ldo regulator general description the RT8234A is a cost effective synchronous buck controller with an integrated 3a linear regulator. the pwm controller provides high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high voltage batteries to generate low voltage supplies in notebook computers. the constant on-time pwm control scheme handles wide input/output voltage ratios with ease and provides ? instant-on ? response to load transients while maintaining a relatively constant switching frequency. the ultra sonic mode (usm) setting maintains the switching frequency above 30khz, which eliminates noise in audio applications. the RT8234A is intended for cpu core, chipset, dram, or other low voltage supplies as low as 0.75v at a reduced cost without the need for a current sense resistor. the 3a ldo regulator maintains fast transient response, only requiring a 20 f ceramic output capacitor. in addition, the ldo supply input is provided by an external power source to significantly reduce the total power loss. the RT8234A is available in a wqfn-16l 3x3 package. features z z z z z pwm controller ` ` ` ` ` wide input voltage range : 4.5v to 26v ` ` ` ` ` adjustable output voltage range : 0. 75v to 3.3v ` ` ` ` ` resistor programmable current limit ` ` ` ` ` quick load step response within 100ns ` ` ` ` ` 1% v out accuracy over line and load ` ` ` ` ` resistor programmable frequency ` ` ` ` ` over/under voltage protection ` ` ` ` ` linear current limit soft-start ` ` ` ` ` drives large synchronous rectifier fets ` ` ` ` ` power good indicator z z z z z ldo regulator ` ` ` ` ` output current up to 3a ` ` ` ` ` 1% accuracy over line and load ` ` ` ` ` adjustable output voltage down to 0.75v ` ` ` ` ` independent enable and power good indicator z z z z z rohs compliant and 100% halogen free ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. pin configurations lout lvin fb pgood phase boot lgate vdd len lpoogd lfb pgnd en cs ugate ton 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd 17 top view wqfn-16l 3x3 marking information 07=ym dnn 07=: product code ymdnn : date code RT8234Agqw 07 ym dnn 07 : product code ymdnn : date code RT8234Azqw RT8234A package type qw : wqfn-16l 3x3 (w-type) lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) free datasheet http:///
RT8234A 2 ds8234a-01 june 2011 www.richtek.com typical application circuit 1 6 1 3 1 2 9 1 v d d e n / m o d e u g a t e f b r t 8 2 3 4 a l g a t e 1 0 1 1 b o o t p h a s e l v i n 3 l o u t v i n p g o o d 2 l p g o o d 7 c s t o n 1 4 v d d c 1 r 5 r t o n r b o o t r u g a t e c b o o t c i n q 1 q 2 r 2 * c 2 * r f b 1 c o u t v o u t r f b 2 c 3 * pgnd 8 c 4 * r f b 4 4 l o u t l f b 6 r f b 3 c l o u t l d o - v o u t r 4 l e n ldo enable 5 1 5 r o c s e t gnd 1 7 ( e x p o s e d p a d ) r 3 * r 6 * c 5 * p g o o d l p g o o d * : o p t i o n a l m o d e s e l e c t i o n p w m e n a b l e / d i s a b l e c l i n free datasheet http:///
RT8234A 3 ds8234a-01 june 2011 www.richtek.com function block diagram pwm controller + - + - 90% v ref lfb lout lpgood len v ref = 0.75v + - ss ramp ss lvin ldo regulator r q s + - comp s1 q latch s1 q latch ov uv 125%v ref 70% v ref + - 90% v ref ss ramp thermal shutdown c.c.m, d.e.m, u.s.m drv drv + - on-time compute 1-shot fb vdd ugate phase vdd pgood pgnd lgate ton boot trig cs - + gm phase 10a - + + - uvlo en/mode min. t off qtrig 1-shot pwm + - gm v ref + free datasheet http:///
RT8234A 4 ds8234a-01 june 2011 www.richtek.com pin no. pin name pin function 1 fb v out feedback input. connect fb to a resistor voltage divider from v out to gnd to adjust the output from 0.75v to 3.3v. 2 pgood power good indicator. it is an open drain output of the internal switch. this pin will be pulled high when the output voltage is within the target range. 3 lvin supply input pin for ldo. 4 lout output terminal of the ldo. 5 len enable input pin for ldo with internal pull low resistor. ldo is enabled if len is greater than the on level and disabled if len is less than the off level. 6 lfb ldo feedback input. connect lfb to a resistive voltage divider from lout to gnd to adjust the output voltage from 0.75v to 3v. 7 lpgood power good indicator. it is an open drain output of ldo regulator. this pin will be pulled high when the output voltage is within the target range. 8 pgnd power ground. 9 lgate low side n-mosfet gate drive output for pwm. this pin swings between pgnd and vdd. 10 vdd supply input pin. gate driver supply for external mosfets and analog supply for the device. bypass to pgnd with a 1 f ceramic capacitor. 11 bo o t bootstrap power pin. this pin powers the high side mosfet driver. connect a bootstrap capacitor between this pin and phase. 12 phase switch node. this pin is not only the current sense input, but also the high side gate driver return. 13 ugate high side n-mosfet gate driver output for pwm. this pin swings between phase and boot. 14 ton on-time setting pin. connect to vin through a resistor. ton is an input of the pwm controller. 15 cs over current set input. connect resistor from this pin to signal ground to set the current limit threshold. 16 en/mode pwm enable, disable and mode selection input. connect this pin to vdd for ccm mode, connect this pin to 3.3v for diode- emulation mode, connect this pin to 2v for ultra sonic mode and connect this pin to gnd for shutdown mode. 17 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. functional pin description free datasheet http:///
RT8234A 5 ds8234a-01 june 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, ton to gnd ------------------------------------------------------------------------------------- ? 0.3v to 32v z boot to phase ---------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z phase to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 1v to 32v <20ns ----------------------------------------------------------------------------------------------------------------------- - ? 8v to 38v z vdd, fb, pgood, en, cs --------------------------------------------------------------------------------------------- ? 0.3v to 6v z ugate to phase dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v <20ns ----------------------------------------------------------------------------------------------------------------------- - ? 5v to 7.5v z lgate to gnd dc -------------------------------------------------------------------------------------------------------------------------- --- ? 0.3v to 6v <20ns ----------------------------------------------------------------------------------------------------------------------- - ? 2.5v to 7.5v z power dissipation, p d @ t a = 25 c wqfn-16l 3x3 ------------------------------------------------------------------------------------------------------------- 1.4 71w z package thermal resistance (note 2) wqfn-16l 3x3, ja ------------------------------------------------------------------------------------------------------- 68 c/w wqfn-16l 3x3, jc ------------------------------------------------------------------------------------------------------- 7.5 c/w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------------- 2kv mm (machine mode) ------------------------------------------------------------------------------------------------------ 200v recommended operating conditions (note 4) z supply input voltage, v in ------------------------------------------------------------------------------------------------ 4.5v to 26v z control voltage, v dd ------------------------------------------------------------------------------------------------------ 4.5v to 5.5v z junction temperature range ------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------------- ? 40 c to 85 c free datasheet http:///
RT8234A 6 ds8234a-01 june 2011 www.richtek.com to be continued (v dd = 5v, v in = 15v, r cs = 100k , r ton = 500k , t a = 25 c, unless otherwise specified) electrical characteristics parameter symbol test conditions min typ max unit pwm controller quiescent supply current fb forced above the regulation point, v cs = 1v -- 0.5 1.25 ma ton operating current r ton = 500k -- 30 -- a v dd (v en = 0v, v len = 0v) -- 3 15 ton -- 1 5 shutdown current i shdn v en = 0v -- 0 -- a fb error comparator threshold (0.75v) v dd = 4.5 to 5.5v dem ? 1 -- 1 % fb input bias current v fb = 0.75v ? 1 0.1 1 a output voltage range v out 0.75 -- 3.3 v on-time, v in = 15v v phase = 1.25v, dem, r ton = 500k 267 334 401 ns minimum off-time v fb = 0.6v 250 400 550 ns minimum on-time 60 -- -- ns current sensing threshold ocset source current 9 10 11 a source current temperature coefficient in comparison with 25 c -- 4700 -- ppm/c cs pin setting range 0.5 -- 2 v zero crossing threshold phase ? gnd ? 13 ? 3 7 mv usm frequency r ton to phase 22 30 -- khz fault protection current limit i lim gnd ? phase, v cs = 2v 180 200 220 mv output uv threshold falling edge 60 70 80 % output uv hysteresis -- 5 -- % ovp threshold rising edge 120 125 130 % ov fault delay fb forced above ov threshold -- 5 -- s under voltage lockout threshold 3.7 3.9 4.1 v under voltage lockout hysteresis falling edge, hysteresis = 300mv, pwm and ldo disabled below this level -- 300 -- mv ramp current limit at soft- sta rt from en high to current limit threshold reaches 100mv -- 1.75 -- ms uv blank time from en signal going high -- 5 -- ms thermal shutdown t sd -- 155 -- c driver on-resistance ugate driver source r ugatesr boot ? phase forced to 5v, ugate high state -- 2 4 ugate driver sink r ugates k boot ? phase forced to 5v, ugate, 10w state -- 1 2 lgate driver source r lgates r lgate, low state -- 1 2 free datasheet http:///
RT8234A 7 ds8234a-01 june 2011 www.richtek.com parameter symbol test conditions min typ max unit l gat e dr ive r sink r lgatesk lgate, low state -- 0.7 1.5 lgate rising (v phase = 1.5v) -- 30 -- dead time ugate rising -- 30 -- ns internal boost charging switch on resistance vdd to boot, 10ma -- -- 80 en logic voltage threshold pwm off -- -- 0.8 pwm on, usm mode 1.7 2 2.3 pwm on, dem mode 2.9 3.3 3.7 en threshold voltage pwm on, ccm mode 4.4 -- -- v pgood (upper side threshold decide by ov threshold) trip threshold (falling) 87 90 93 trip hysteresis measured at fb, with respect to reference, no load -- 3 -- % fault propagation delay falling edge, fb forced below pgood trip threshold -- 2.5 -- s output low voltage i sink = 1ma -- -- 0.4 v leakage current i leak high state, forced to 5v -- -- 1 a ldo regulator ldo quiescent current i q pwm off, ldo on, i out = 0ma -- -- 400 a ldo current limit i ldooc v lvin = 1.8v, v lout = 1.05v, v lfb = 0.7v 3.1 4.5 -- a fold back short current v lvin = 1.8v, v lfb < 0.375v -- 1.8 -- a soft-start time t ss from len high to internal v ref reaches 0.71v -- 3 -- ms ldo pgood delay time from len high to lpgood high -- 6 -- ms ldo feedback 0.7425 0.75 0.7575 v dropout voltage v drop i out = 2a, v lout = 1.05v -- -- 300 mv load regulation v load 0a < i ldo < 3a, v dd = 5v, v lvin = v lout + 1 v -- -- 1 % line regulation v line_in v dd = 5 v, v lvi n = v lout + 1v to 5v, i ldo = 1ma -- -- 0.6 % ldo discharge resistance i ldodischg v len = 0v, v lout = 0.5v -- -- 50 logic-high v len_h ldo on 2 -- -- len threshold voltage logic-low v len_l ldo off -- -- 0.8 v len input current i len v len = 5v (internal pull low) -- -- 10 a lfb input current i lfb ? 1 -- 1 a lpgood threshold 87 90 93 % lpgood hysteresis measured at lfb, with respect to reference, no load. -- 3 -- % lpgood propagation delay -- 2.5 -- s lpgood low voltage i sink = 1ma -- -- 0.4 v free datasheet http:///
RT8234A 8 ds8234a-01 june 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings, functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. free datasheet http:///
RT8234A 9 ds8234a-01 june 2011 www.richtek.com typical operating characteristics efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 100 load current (a) efficiency (%) efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 100 load current (a) efficiency (%) efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 100 load current (a) efficiency (%) switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 325 0.001 0.01 0.1 1 10 100 load current (a) switching frequency (khz) 1 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 325 0.001 0.01 0.1 1 10 100 load current (a) switching frequency (khz) 1 switching frequency vs. load current 0 25 50 75 100 125 150 175 200 225 250 275 300 325 0.001 0.01 0.1 1 10 100 load current (a) switching frequency (khz) 1 v in = 8v dem usm ccm v in = 12v dem usm ccm v in = 20v dem usm ccm v in = 8v dem usm ccm v in = 20v dem usm ccm v in = 12v dem usm ccm free datasheet http:///
RT8234A 10 ds8234a-01 june 2011 www.richtek.com quiescent current vs. input voltage 480 500 520 540 560 580 600 620 640 660 680 4 6 8 101214161820222426 input voltage (v) quiescent current (a ) shutdown current vs. input voltage 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 4 6 8 101214161820222426 input voltage (v) shutdown current (a) 1 v en = 5v, no load pwm pwm + ldo en = gnd, no load time (1ms/div) power on from en/mode (usm) time (400ms/div) power off from en/mode (ccm) v in = 12v, v en = 5v, no load time (1ms/div) power on from en/mode (ccm) en/mode (3v/div) v out (1v/div) ugate (20v/div) pgood (5v/div) v in = 12v, v en = 3v, no load time (1ms/div) power on from en/mode (dem) en/mode (3v/div) v out (1v/div) ugate (20v/div) pgood (5v/div) v in = 12v, v en = 2v, no load en/mode (3v/div) v out (1v/div) ugate (20v/div) pgood (5v/div) v in = 12v, v en = gnd, no load en/mode (3v/div) v out (1v/div) ugate (20v/div) pgood (5v/div) free datasheet http:///
RT8234A 11 ds8234a-01 june 2011 www.richtek.com ldo current vs. temperature 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -50 -25 0 25 50 75 100 125 temperature (c) ldo current (a) ldo dropout voltage vs. load current 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 load current (a) dropout voltage (v) time (10 s/div) vout load transient response i l (10a/div) v out_ac (100mv/div) ugate (20v/div) lgate (10v/div) time (20 s/div) ovp v lvin = 1.8v, v len = 5v, v lout = 1.05v v lvin = 3.3v, c out = 10 f x 2, i out = 0a to 3a, v lout = 1.05v time (100 s/div) ldo load transient response i load (2a/div) v out_ldo ac-coupled (50mv/div) time (20 s/div) uvp v len = 5v v in = 12v, v en = 5v, i out = 0a to 20a, v out = 1.5v pgood (5v/div) v out (1v/div) ugate (10v/div) lgate (10v/div) v in = 12v, v en = 5v, no load inductor current (20a/div) v out (1v/div) lgate (10v/div) v in = 12v, v en = 5v, no load ugate (20v/div) 125 c 25 c ? 40 c current limit fold back short free datasheet http:///
RT8234A 12 ds8234a-01 june 2011 www.richtek.com time (1ms/div) ldo power on from len len (5v/div) lout (1v/div) lpgood (5v/div) time (1ms/div) ldo power off from len v lvin = 1.5v, c in = 10 f, c out = 10 f x 2, no load v lvin = 1.5v, c in = 10 f, c out = 10 f x 2, no load len (5v/div) lout (1v/div) lpgood (5v/div) free datasheet http:///
RT8234A 13 ds8234a-01 june 2011 www.richtek.com application information overview the RT8234A pwm controller provides high efficiency, excellent transient response, and high dc output accuracy needed for stepping down high voltage batteries to generate low voltage cpu core, i/o, and chipset ram supplies in notebook computers. richtek mach response tm technology is specifically designed for providing 100ns ? rinstant-on ? response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. the topology circumvents the poor load transient timing problems of fixed-frequency current-mode pwms while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant off-time pwm schemes. the drv tm mode pwm modulator is specifically designed to have better noise immunity for such a single output application. pwm operation the output ripple valley voltage is monitored at a feedback point voltage. refer to the function diagrams of RT8234A, the synchronous high side mosfet is turned on at the beginning of each cycle. after the internal one-shot timer expires, the mosfet is turned off. the pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. another one-shot sets a minimum off-time (400ns typ.). on-time control the on-time one-shot comparator has two inputs. one input monitors the output voltage from the phase pin, while the other input samples the input voltage and converts it to a current. this input voltage proportional current is used to charge an internal on-time capacitor. the on-time is the time required for the voltage on this capacitor to charge from zero volts to vout, thereby making the on- time of the high side switch directly proportional to the output voltage and inversely proportional to the input voltage. this implementation results in a nearly constant switching frequency without the need for a clock generator. the on-time is set according to below equation : t on = [v o x 3.53 / (v in ? 0.9) ] x r ton x 2 + 33ns; r ton connects to v in and the switching frequency is : f = v out / (v in x t on ) there is a minimum on-time about 60ns to ensure that the output voltage can start up from 0v. enable and disable the en/mode pin allows for power sequencing between the controller bias voltage and another voltage rail. the RT8234A remains in shutdown if the en pin is lower than 800mv. when en/mode pin rises above the v en trip point, the RT8234A will begin a new initialization and soft- start cycle. por, uvlo and soft-start power on reset (por) occurs when vdd rises above to approxim ately 4.2v, the r t8234a will reset the fault latch and prepare the pwm for operation. below 3.7v (min), the vdd under voltage lockout (uvlo) circuitry inhibits switching by keeping ugate and lgate low. a built-in soft-start is used to prevent surge current from power supply input after pwm is enabled. a ramping up current limit threshold can eliminate the v out folded-back while in the soft-start duration. mode selection (en/mode) operation operation mode is set according to the enable voltage level. when v en is set from 4.4v to 5.5v, the controller operates in ccm. when v en is set from 2.9v to 3.7v, the controller operates in diode emulation mode. finally, when v en is from 1.7v to 2.3v, the controller operates in ultrasonic mode. ultrasonic mode (v en from 1.7v to 2.3v) the RT8234A activates a unique diode-emulation mode with a minimum switching frequency of 30khz, called the ultrasonic mode. the ultrasonic mode avoids audio frequency modulation that would otherwise be present when a lightly loaded controller automatically skips free datasheet http:///
RT8234A 14 ds8234a-01 june 2011 www.richtek.com pulses. in ultrasonic mode, the high side switch gate driver signal is or with an internal oscillator (>30khz). once the internal oscillator is triggered, the controller enters constant off-time control. when output voltage reaches the setting peak threshold, the controller turns on the low side mosfet until the controller detects that the inductor current has dropped below the zero crossing threshold. the internal circuitry provides a constant off-time control, and it is effective to regulate the output voltage under light load condition. diode-emulation mode (v en from 2.9v to 3.7v) when v en is set from 2.9v to 3.7v, the controller operates in diode-emulation mode. in diode-emulation mode, the RT8234A automatically reduces switching frequency at light-load conditions to maintain high efficiency. this reduction of frequency is achieved smoothly without increasing vout ripple or load regulation. as the output current decreases from heavy-load condition, the inductor current is also reduced and eventually reaches the point where its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. by emulating the behavior of diodes, the low side mosfet allows only partial negative current when the inductor freewheeling current reaches negative. as the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that requires the next ? on ? cycle. the on-time is kept the same as that in the heavy- load condition. in reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. the transition load point to the light load operation can be calculated as follows (figure 1) : where t on is the on-time. () ? ? in out load on v v i t 2l figure 1. boundary condition of ccm/dcm i l t 0 t on slope = (v in - v out ) / l i l, peak i load = i l, peak / 2 the switching waveforms may appear noisy and asynchronous when light loading causes diode-emulation operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in dem noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. the disadvantages for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). forced-ccm mode (v en from 4.4v to 5.5v) the low noise, forced-ccm mode (v en from 4.4v to 5.5v) disables the zero-crossing comparator, which controls the low side switch on-time. this causes the low side gate drive waveform to become the complement of the high side gate drive waveform. this in turn causes the inductor current to reverse at light loads as the pwm loop to maintain a duty ratio vout/vin. the benefit of forced- ccm mode is maintenance of a fairly constant switching frequency, but it comes at a cost. the no load battery current can be anywhere from 10ma to 40ma, depending on the external mosfets. current limit setting (cs) the RT8234A has cycle-by-cycle current limiting control. the current limit circuit employs a unique ? valley ? current sensing algorithm. if the magnitude of the current-sense signal at phase is above the current limit threshold, the pwm is not allowed to initiate a new cycle (figure 2). in order to provide both good accuracy and a cost effective solution, the RT8234A supports temperature compensated mosfet r ds(on) sensing. free datasheet http:///
RT8234A 15 ds8234a-01 june 2011 www.richtek.com the current limit threshold is equal to 1/10 of the voltage at this pin. choose a current limit resistor by following below equation: r ocset = (i ilimt x r ds(on) ) x 10 / 10 a the inductor current is monitored by the voltage between the gnd pin and the phase pin, so the phase pin should be connected to the drain terminal of the low side mosfet. i ocset has a temperature coefficient to compensate the temperature dependency of the r ds(on) . gnd is used as the positive current sensing node so gnd should be connected to the source terminal of the bottom mosfet. as the comparison is being done during the off state, v ilimt (current limit threshold) sets the valley level of the inductor current. thus, the load current at over current threshold, i ilimp , can be calculated as follows : in an over current condition, the current to the load exceeds the current to the output capacitor. thus, the output voltage tends to fall. eventually it crosses the under voltage protection threshold and shuts down. ? ilimt ripple ilimp ds(on) in out out ilimt ds(on) in vi i = + r2 (v v ) v v 1 = + r2lf v figure 2. ? valley ? current limit i l t 0 i l, peak i limit i load mosfet gate driver the high side driver is designed to drive high current, low r ds(on) n-mosfet(s). when configured as a floating driver, 5v bias voltage is delivered from the vdd supply. the average drive current is proportional to the gate charge at v gs = 5v times switching frequency. the instantaneous drive current is supplied by the flying capacitor between boot and phase pins. a dead time to prevent shoot through is internally generated between high side mosfet off to low side mosfet on, and low side mosfet off to high side mosfet on. the low side driver is designed to drive high current, low r ds(on) n- mosfet(s). the internal pull-down transistor that drives lgate low is robust, w ith a 0.7 typical on- resistance. a 5v bias voltage is delivered from the vdd supply. the instantaneous drive current is supplied by the flying capacitor between vdd and gnd. for high current applications, some combinations of high and low side mosfets that will cause excessive gate- drain coupling may be encountered, which can lead to efficiency-killing, emi-producing shoot-through currents. this is often remedied by adding a resistor in series with boot, which increases the turn-on time of the high side mosfet without degrading the turn-off time (figure 3). boot ugate phase r v in figure 3. reducing the ugate rise time power good output (pgood) the power good output is an open-drain output and requires a pull-up resistor. when the output voltage is 25% above or 10% below its set voltage, pgood gets pulled low. it is held low until the output voltage returns to within these tolerances once more. during soft-start, pgood is actively held low and only allowed to transition high when soft- start is over and the output reaches 90% of its set voltage. there is a 2.5 s delay built into the pgood circuitry to prevent false transition. output over voltage protection (ovp) the output voltage can be continuously monitored for over voltage protection. when the output voltage exceeds 25% of its set voltage threshold, over voltage protection is triggered and the low side mosfet is latched on. this activates the low side mosfet to discharge the output capacitor. the RT8234A is latched once ovp is triggered and can only be released by vdd or en power on reset. there is a 5 s delay built into the over voltage protection circuit to prevent false transitions. free datasheet http:///
RT8234A 16 ds8234a-01 june 2011 www.richtek.com output under voltage protection (uvp) the output voltage can be continuously monitored for under voltage protection. when the output voltage is less than 70% of its set voltage threshold, under voltage protection is triggered and then both ugate and lgate gate drivers are forced low. in order to remove the residual charge on the output capacitor during the under voltage period, if phase is greater than 0.75v, lgate is forced high until phase is lower than 0.75v. there is a 2.5 s delay built into the under voltage protection circuit to prevent false transitions. during soft-start, the uvp blanking time is 5ms. output voltage setting (fb) the output voltage can be adjusted from 0.75v to 3.3v by setting the feedback resistors, r1 and r2 (figure 4). choose r2 to be approximately 10k , and solve for r1 using the below equation : figure 4. setting v out with a resistive voltage divider where v fb is 0.75v. r1 r2 v out fb inductor selection the inductor plays an important role in step-down converters because the energy from the input power rail is stored in it and then released to the load. from the viewpoint of efficiency, the dc resistance (dcr) of inductor should be as small as possible to minimize the conduction loss. in addition, because the inductor takes up most of the board space, its size is also important. low profile inductors can save board space especially when the height has limitation. however, low dcr and low profile inductors are usually cost ineffective. additionally, larger inductance results in lower ripple current, which means lower power loss. however, the inductor current rising time increases with inductance value. this means the transient response will be slower. therefore, the inductor design is a trade-off between performance, size and cost. in general, the inductance is designed such that the ripple current ranges between 20% to 40% of full load current. the inductance can be calculated using the following equation : ? = in out out min sw out_rated in vv v l fki v ?? ?? ?? out fb r1 v = v 1+ r2 where k is the ratio between inductor ripple current and rated output current. input capacitor selection voltage rating and current rating are the key parameters when selecting input capacitor. generally, the input capacitor should have a voltage rating 1.5 times greater than the maximum input voltage to be considered a conservatively safe design. the input capacitor is used to supply the input rms current, which can be approximately calculated using the following equation : ?? = ? ?? ?? out out rms out in in vv ii 1 vv the next step is selecting a proper capacitor for rms current rating. using more than one capacitor with low equivalent series resistance (esr) in parallel to form a capacitor bank is a good design. besides, placing ceramic capacitor close to the drain of the high side mosfet is helpful in reducing the input voltage ripple at heavy load. output capacitor selection the output filter capacitor must have esr low enough to meet output ripple and load-transient requirement, yet have high enough esr to satisfy stability requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the ovp circuit. for cpu core voltage converters and other applications where the output is subject to violent load transient, the output capacitor's size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance : p-p load(max) v esr i free datasheet http:///
RT8234A 17 ds8234a-01 june 2011 www.richtek.com in non-cpu applications, the output capacitor's size depends on how much esr is needed to maintain at an acceptable level of output voltage ripple : p-p ir load(max) v esr li sw esr out f 1 f = 2 esr c 4 organic semiconductor capacitors or specially polymer capacitors are recommended. output capacitor stability stability is determined by the value of the esr zero relative to the switching frequency. the point of instability is given by the following equation : do not put high-value ceramic capacitors directly across the outputs without taking precautions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic and unstable operation. however, it is easy to add sufficient series resistance by placing the capacitors a couple of inches downstream from the inductor and connecting v out or fb divider close to the inductor. there are two related but distinct ways including double- pulsing and feedback loop instability to identify the unstable operation. double-pulsing occurs due to noise on the output or because the esr is too low that there is not enough voltage ramp in the output voltage signal. the ? fools ? the error comparator into triggering a new cycle immediately after 400ns minimum off-time period has expired. double- pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it may indicate the possible presence of loop instability, which is caused by insufficient esr. loop instability can result in oscillation at the output after line or load perturbations that can trip the over voltage protection latch or cause the output voltage to fall below the tolerance limit. the easiest method for stability checking is to apply a very zero-to-max load transient and carefully observe the output-voltage-ripple envelope for overshoot and ringing. it helps to simultaneously monitor the inductor current with ac probe. do not allow more than one ringing cycle after the initial step-response under- or over-shoot. mosfet selection the majority of power loss in the step-down power conversion is due to the loss in the power mosfets. for low voltage high current applications, the duty cycle of the high side mosfet is small. therefore, the switching loss of the high side mosfet is of concern. power mosfets with lower total gate charge are preferred in such kind of application. however, the small duty cycle means that the low side mosfet is on for most of the switching cycle. therefore, the conduction loss tends to dominate the total power loss of the converter. to improve overall efficiency, mosfets with low r ds(on) are preferred in the circuit design. in some cases, more than one mosfet are connected in parallel to further decrease the on-state resistance. however, this depends on the low side mosfet driver capability and the budget. ldo normal operation the RT8234A includes a built-in n-mosfet ldo. it provides current up to 3a, from a 1.5v to 3.3v ldo input. vdd powers the ldo internal circuitry. like any low-dropout regulator, the device requires input and output decoupling capacitors. please note that linear regulators with a low dropout voltage have high internal loop gains which require care in guarding against oscillation caused by insufficient decoupling capacitance. ldo input and output capacitor selection like any low-dropout regulator, the external capacitors used with the built-in ldo must be carefully selected for regulator stability and performance. use a capacitor with value >10 f on the ldo input and the amount of capacitance can be increased. the input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the ic and returned to a clean analog ground. any good quality ceramic can be used for this capacitor. a capacitor with larger value and lower esr (equivalent series resistance) will provide better line transient response. the RT8234A ldo is designed specifically to work with ceramic output capacitor in space saving and performance consideration. using a ceramic capacitor with value of at least 20 f on the ldo output will ensure stability. output free datasheet http:///
RT8234A 18 ds8234a-01 june 2011 www.richtek.com over current or short circuit, over current protection function will activate and override the voltage regulation function to limit the output current at 4.5a (typical). if over current or short circuit is not removed, large power dissipation at this condition may also cause chip temperature to rise and trigger the over temperature protection. package power dissipation the device implements an internal thermal shutdown feature to protect itself if junction temperature exceeds 155 c. when the junction temperature exceeds the thermal shutdown threshold, the otp function will be triggered and the RT8234A will shut down and entrer latch- off mode. in latch-off mode, the RT8234A can only be reset by en/len or power input vdd. the RT8234A is a synchronous buck controller with 3a linear regulator. the main source of power dissipation on the package is the mosfet driver and the ldo. the total power dissipation must not exceed the maximum allowable power dissipation for the wqfn-16l package. calculating the power dissipation for both driver and ldo is crucial to ensure a safe operation of the controller. exceeding the maximum allowable power dissipation will cause the ic to be operated beyond the recommended maximum junction temperature of 125 c. the maximum power dissipation for the wqfn-16l package is approximately equal to 1.47w at room temperature. the following equations provide the estimation of power dissipation of the integrated drivers and ldo. t j = t a + ( ja x p d ) where n hs and n ls are the number of high side mosfet and the low side mosfet. c ugate and c lgate represent c iss of the high side mosfet and the low side mosfet, respectively. v lvin is the ldo input voltage and v lvout is the ldo output voltage. from above equations, it is clear that the junction temperature is directly proportional to the total c iss of all the external mosfets and ldo power dissipation. ( ) () ? ? 2 d hs ugate boot phase sw ls lgate cc sw lvin lvout out p = n c v f + n c v f +(v v ) ldoi ?? ?? ?? lout lfb r3 v = v 1+ r4 capacitor of larger capacitance can reduce noise and improve load transient response, stability, and psrr. the output capacitor should be located at not more than 0.5 inch from the lout pin of the RT8234A and returned to a clean analog ground. ldo output voltage setting the lfb pin connects directly to the inverting input of the error amplifier and the output voltage is set using external resistors, r3 and r4 (figure 5). the following equation is for adjusting the output voltage. where v lfb is 0.75v (typ.). r3 r4 v lout lfb figure 5. setting v lout with a resistive voltage divider ldo enable the RT8234A ldo is shut down by pulling the len pin lower than 800mv and turned on by pulling the len pin above the v len_h trip point. if the shutdown feature is not required, the len pin should be tied to lvin to keep the regulator on at all times (the len pin must not be left floating). ldo power good output (lpgood) the power good output is an open-drain output and requires a pull-up resistor. when the ldo output voltage is 25% above or 10% below its set voltage, lpgood gets pulled low. it is held low until the output voltage returns to within these tolerances once more. during soft-start, lpgood is actively held low and allowed to transition high only after soft-start is over and the output reaches 90% of its set voltage. there is a 2.5 s delay built into lpgood circuitry to prevent false transition. ldo current limit the RT8234A continuously monitors the ldo output current for over current protection. in the event of output free datasheet http:///
RT8234A 19 ds8234a-01 june 2011 www.richtek.com thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8234A, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn- 16l 3x3 packages, the thermal resistance, ja , is 68 c/ w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c ) / (68 c/w) = 1.471w for wqfn-16l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j (max) and thermal resistance, ja . for the RT8234A package, the derating curve in figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 6. derating curve for the RT8234A package layout considerations layout is very important in high frequency switching converter design. if designed improperly, the pcb could radiate excessive noise and contribute to converter instability. certain points must be considered before starting a layout for the RT8234A. ` connecting capacitors to vdd, lvin, lout are recommended. place these capacitors close to the ic. ` keep current limit setting network as close as possible to the ic. routing of the network should avoid coupling to high voltage switching node. ` connections from the drivers to the respective gate of the high side or the low side mosfet should be as short as possible to reduce stray inductance. ` all sensitive analog traces and components such as fb, lfb, gnd, pgnd, en, len, cs, pgood, lpgood, vdd, and ton should be placed away from high voltage switching nodes such as phase, lgate, ugate, or boot nodes to avoid coupling. use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. ` current sense connections must always be made using kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. ` power sections should connect directly to ground plane(s) using multiple vias as required for current handling (including the chip power ground connections). power components should be placed to minimize loops and reduce losses. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb free datasheet http:///
RT8234A 20 www.richtek.com ds8234a-01 june 2011 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 free datasheet http:///

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